By way of example, FIG. 1 depicts a timing sequence 100 of two clock domains having an N:(N−1) frequency ratio wherein data transfer across the clock boundary between the domains results in an extra data cycle or “dead cycle” in which data cannot be transferred. As is well known, data transfer operations between circuitry of a first clock domain and circuitry of a second clock domain are effectuated by synchronizer circuitry disposed therebetween. Further, the first and second clock domains are operable with clock signals that have a particular cycle ratio. For instance, the circuitry of the first clock domain (“fast clock domain”) may be clocked with a first clock signal (CLK1) that is faster than a second clock signal (CLK2) used for clocking the circuitry of the second clock domain (“slow clock domain”) such that there are N first clock cycles to (N−1) second clock cycles. In one application, core clock circuitry and bus clock circuitry of a computer system may represent the first and second clock domains, respectively, wherein CLK1 and CLK2 signals correspond to the core clock (CC) and bus clock (BC) signals.
A synchronizer controller circuit (not shown in FIG. 1) is usually provided for controlling the operation of synchronizer circuitry disposed between the two clock domains. Additionally, a control signal such as a SYNC pulse may be generated based on a predetermined temporal relationship between CLK1 and CLK2 for synchronizing the data transfer operations. For example, the SYNC pulse may be generated when a rising edge of the CLK1 signal coincides with a rising edge of the CLK2 signal, which commences a data transmit window for the transfer of data blocks, which may include one or more data bits, from one clock domain to the other clock domain.
The timing sequence 100 of FIG. 1 illustrates an embodiment of CLK1 104, CLK2 106 and SYNC pulse signal 108, wherein for every five ticks of CLK1 there are four ticks of the slow clock (i.e., CLK2). A cycle count 102 refers to the numbering of CLK1 cycles in a particular data transmit window of the timing sequence 100. Data to be transferred from the fast clock domain is clocked at CLK1, that is, 5 data block pulses per window are available.
As alluded to before, the SYNC pulse 108 is high on coincident rising edges of CLK1 and CLK2 and the data transfer operations across the clock boundary between the two clock domains are timed with reference to the SYNC pulse. In a normal condition where there is no skew (or, jitter, as it is sometimes referred to) between CLK1 and CLK2, the coincident edges occur on the rising edges of the first cycle (cycle 0) as shown in FIG. 1. Since there are five CLK1 cycles and only four CLK2 cycles, CLK1 domain circuit portion cannot transmit data during one cycle resulting in what is known as a “dead tick,” as CLK2 domain circuit portion does not have a corresponding time slot for receiving it. Typically, the cycle that is least skew tolerant is the one where data is not transmitted and, in the exemplary timing sequence shown in FIG. 1, it is the fourth cycle (i.e., cycle 3).
Skew between CLK1 and CLK2 signals can cause, for example, a variance in the positioning of the SYNC pulse which affects the data transfer operations between CLK1 and CLK2 domains. In the exemplary 5:4 frequency ratio scenario set forth above, if CLK2 leads CLK1 by a quarter cycle for instance, then instead of the edges being coincident at the start of cycle 0, they will be coincident at the start of cycle 1 and the dead tick's location may accordingly vary. In similar fashion, if CLK2 lags CLK1 by a quarter cycle, the edges will be coincident at the start of the last cycle (i.e., cycle 4). Regardless of the skew between the clock cycles, however, there will be a cycle where a data block cannot be sent, resulting in data transfer at less than full bandwidth. Furthermore, in channelized data transmission scenarios, where multiplexed data blocks are transmitted from a fast clock domain to a slow clock domain sequentially as contiguous data blocks, the latency introduced by dead cycles presents problems. Additionally, these problems can be particularly limiting where header blocks associated with multiplexed data blocks require excessive processing time.